Several efforts are underway to use silicon planar processing to fabricate large arrays of extrinsic silicon infrared (IR) detectors. Arrays of thousands of detectors are required for future IR imaging systems, and cost considerations will require large scale integration in planar silicon wafers which are doped with appropriate impurities to attain IR sensitivity wherein the detectors are not delineated, and optical and electrical cross-talk severely limit the density of the detectors.
Special efforts are also required to delimit the dopant materials used in the detectors from entering the CCD structures which are a part of the same silicon wafer. Selection of the dopant materials are restricted to those which diffuse very slowly at temperatures (1000.degree. -1200.degree. ) commonly used in silicon CCD processing. The only known 3-5 micrometer wavelength dopant which may be compatible with the CCD structure is the metal indium. This dopant is a very slow diffusant in silicon, has low solubility, and thus has low optical absorption in silicon. This is very restrictive since slow diffusant dopants at the 1000.degree. -1200.degree. C CCD processing temperature generally have low solubility. Thus efficient extrinsic silicon detectors must be very thick to be efficient since optical absorption is otherwise very small. If the detectors are thick, the optical and electrical cross-talk will be severe.
The apparatus of the present invention overcomes these problems since there is complete chemical isolation of the detectors from the CCD structure and thus the dopant is not limited to indium by may include a wide variety of either slow or rapid diffusant dopants that are incompatible with the CCD structure. Also, the SOS based structure will eliminate optical and electrical cross-talk and permit very close spacing of the detectors in the focal plane of the IR imager.